IC62LV256L Datasheet, PDF (5/9 Pages) Integrated Circuit Solution Inc – 32K x 8 Low Power SRAM with 3.3V

IC62LV256L
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
-15 ns
-20 ns
-25 ns
Min. Max.
Min. Max.
Min. Max.
Unit
tRC
Read Cycle Time
15 —
20 —
25 —
ns
tAA
Address Access Time
— 15
— 20
— 25
ns
tOHA
tACE
tDOE
tLZOE⁽²⁾
tHZOE⁽²⁾
tLZCE⁽²⁾
tHZCE⁽²⁾
tPU⁽³⁾
tPD⁽³⁾
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
CE to Power-Down
2—
2—
2—
ns
— 15
— 20
— 25
ns
—7
—8
—9
ns
0—
0—
0—
ns
—8
—9
— 10
ns
3—
3—
3—
ns
—6
—9
— 10
ns
0—
0—
0—
ns
— 15
— 18
— 20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3.3V
635 Ω
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
702 Ω
3.3V
635 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
702 Ω
Integrated Circuit Solution Inc.
5
ALSR008-0A 10/5/2001