IC62VV25616LL Datasheet, PDF (2/11 Pages) Integrated Circuit Solution Inc – 256Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM

IC62VV25616L
IC62VV25616LL
256K x 16 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access times: 55, 70, 100 ns
• CMOS low power operation
ICC1=10mA (typical)* operating
ISB2=1µA (typical)* CMOS standby
* Typical values are measured at VCC=1.8V,
TA=25°C
• TTL compatible interface levels
• Single 1.65V-2.2V Vcc power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP-2 and 48-pin
6*8mm TF-BGA
DESCRIPTION
The ICSI IC62VV25616L and IC62VV25616LL are low-power,
4.194,304 bit static RAMs organized as 262,144 words by 16
bits. They are fabricated using ICSI's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When CE is HIGH (deselected) or both LB and UB are HIGH,
the device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC62VV25616L and IC62VV25616LL are packaged in the
JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE
OE
CONTROL
WE
CIRCUIT
UB
LB
COLUMN I/O
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2001, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001