IC41C1665 Datasheet, PDF (2/19 Pages) Integrated Circuit Solution Inc – 64K x16 bit Dynamic RAM with Fast Page Mode

IC41C1665
IC41LV1665
64K x 16 (1-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
DESCRIPTION
• Fast access and cycle time
• TTL compatible inputs and outputs
• Refresh Interval: 256 cycles/4 ms
• Refresh Mode: RAS-Only, CAS-before-RAS
(CBR), Hidden
• JEDEC standard pinout
• Single power supply:
— 5V ± 10% (IC41C1665)
— 3.3V ± 10% (IC41LV1665)
The ICSI IC41C1665 and the IC41LV1665 are 65,536 x 16-
bit high-performance CMOS Dynamic Random Access
Memory. Fast Page Mode allows 256 random accesses
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
byte, makes these devices ideal for use in 16-, 32-bit wide
data bus systems.
These features make the IC41C1665 and the IC41LV1665
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
• Byte Write and Byte Read operation via
two CAS
The IC41C1665 and the IC41LV1665 are packaged in a 40-
pin, 400mil SOJ and TSOP-2.
• Available in 40-pin SOJ and TSOP-2
KEY TIMING PARAMETERS
PIN CONFIGURATIONS
40-Pin TSOP-2
Parameter
-25 -30 -35 -40 Unit
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
25 30 35 40 ns
8 9 10 11 ns
Max. Column Address Access Time (tAA) 12 16 18 20 ns
Min. Fast Page Mode Cycle Time (tPC) 15 20 23 25 ns
Min. Read/Write Cycle Time (tRC)
43 55 65 75 ns
40-Pin SOJ
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
VCC 20
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 NC
25 A7
24 A6
23 A5
22 A4
21 GND
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
VCC 20
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 NC
25 A7
24 A6
23 A5
22 A4
21 GND
PIN DESCRIPTIONS
A0-A7
I/O0-I/O15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address
Strobe
Lower Column Address
Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001