IS61LV6432 Datasheet, PDF (10/16 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

IS61LV6432
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-166
-133
-117
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
6 — 7.5 — 8.5 — 10 — 12 — 13 — 15 — ns
tKH
Clock High Time
2.4 — 2.8 — 3.0 — 3.5 — 4 — 6 — 6 — ns
tKL
Clock Low Time
2.4 — 2.8 — 3.0 — 3.5 — 4 — 6 — 6 — ns
tAS
Address Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS
Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS
Write Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tDS
Data In Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tDH
Data In Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH
Write Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCFG
Notes:
Configuration Setup⁽¹⁾
25 — 30 — 35 — 35 — 45 — 52 — 60 — ns
1. Configuration signal MODE is static and must not change during normal operation.
10
Integrated Circuit Solution Inc.
SSR005-0B