IC41C82052 Datasheet, PDF (1/18 Pages) Integrated Circuit Solution Inc – 2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

IC41C82052
IC41LV82052
2M x 8 (16-MBIT) DYNAMIC RAM
WITH .AST PAGE MODE
.EATURES
• .AST Page Mode access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: 4)5-Only,
+)5-before-4)5 (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V±10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
+)5
DESCRIPTION
The 1+51 82052 Series is a 2,097,152 x 8-bit high-performance
CMOS Dynamic Random Access Memory. The .ast Page
Mode allows 2,048 random accesses within a single row with
access cycle time as short as 20 ns per 8-bit word.
These features make the 82052 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 82052 Series is packaged in a 28-pin 300mil SOJ and a 28
pin TSOP-2
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IC41C82052
2K
5V ± 10%
IC41LV82052
2K
3.3V ± 10%
PIN CON.IGURATION
28 Pin SOJ, TSOP-2
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
WE 6
RAS 7
NC 8
A10 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28 GND
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 GND
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
-50 -60 Unit
50 60 ns
13 15 ns
25 30 ns
20 25 ns
84 104 ns
PIN DESCRIPTIONS
A0-A10
I/O0-7
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
1
DR015-0A 06/12/2001