IC-LFS_15 Datasheet, PDF (7/10 Pages) IC-Haus GmbH – 32x1 LINEAR IMAGE SENSOR

iC-LFS
32x1 LINEAR IMAGE SENSOR
DESCRIPTION OF FUNCTIONS
Rev A2, Page 7/10
Normal operation
Following an internal power-on reset the integration
and hold capacitors are discharged and the sample
and hold circuit is set to sample mode. A high signal
at SI and a rising edge at CLK triggers a readout cycle
and with it a new integration cycle.
In this process the hold capacitors of pixels 1 to 31
are switched to hold mode immediately (SNH = 1), with
pixel 32 (SNH32 = 1) following suit one clock pulse later.
This special procedure allows all pixels to be read out
with just 32 clock pulses. The integration capacitors are
discharged by a one clock long reset signal (NRCI = 0)
which occurs between the 2^nd and 3^rd falling edge of
the readout clock pulse (cf. Figure 4). After the 31 pix-
els have been read out these are again set to sample
mode (SNH = 0), likewise for pixel 32 one clock pulse
later (SNH32 = 0).
30
31
32
1
2
3
4
...
CLK
31
32
1
2
SI
V(AO)
Pix30 Pix31
Pix32
Pix1
Pix2
Pix3
...
Pix31 Pix32
Pix1
SNH
SNH32
NRCI
Integration Time Pixel 1−31
Integration Time Pixel 32
Figure 4: Readout cycle and integration sequence
If prior to the 32^th clock pulse a high signal occurs pacitors retain their old value i.e. hold mode prevails
at SI the present readout is halted and immediately (SNH/SNH32 = 0).
reinitiated with pixel 1. In this instance the hold ca-
30 31 32 1
2
3
4
5
1
2
3
4
...
32
1
2
CLK
SI
V(AO)
Pix30 Pix31 Pix32 Pix1
Pix2
Pix3
Pix4
Pix5 Pix1
Pix2
Pix3
Pix4
... Pix32
Pix1
SNH
SNH32
NRCI
Figure 5: Restarting a readout cycle
With more than 32 clock pulses until the next SI signal, put voltage tracks the voltage of the pixel 1 integration
pixel 1 is output without entering hold mode; the out- capacitor.