IC-LFM Datasheet, PDF (6/9 Pages) IC-Haus GmbH – 64x1 LINEAR IMAGE SENSOR

iC-LFM
64x1 LINEAR IMAGE SENSOR
DESCRIPTION OF FUNCTIONS
preliminary
Rev A0.2, Page 6/9
Normal operation
Following an internal power-on reset the integration
and hold capacitors are discharged and the sample
and hold circuit is set to sample mode. A high signal
at SI and a rising edge at CLK triggers a readout cycle
and with it a new integration cycle.
In this process the hold capacitors of pixels 1 to 63 are
switched to hold mode immediately (SNH = 1), with
pixel 64 (SNH64 = 1) following suit one clock pulse
later. This special procedure allows all pixels to be
read out with just 64 clock pulses. The integration ca-
pacitors are discharged by a one clock long reset sig-
nal (NRCI = 0) which occurs between the 2^nd and 3^rd
falling edge of the readout clock pulse (cf. Figure 4).
After the 63 pixels have been read out these are again
set to sample mode (SNH = 0), likewise for pixel 64
one clock pulse later (SNH64 = 0).
62
63
64
1
2
3
4
...
CLK
63
64
1
2
SI
V(AO)
Pix62 Pix63
Pix64
Pix1
Pix2
Pix3
...
Pix63 Pix64
Pix1
SNH
SNH64
NRCI
Integrationszeit Pixel 1−63
Integrationszeit Pixel 64
Figure 4: Readout cycle and integration sequence
If prior to the 64^th clock pulse a high signal occurs
at SI the present readout is halted and immediately
re-initiated with pixel 1. In this instance the hold ca-
pacitors retain their old value i.e. hold mode prevails
(SNH/SNH64 = 0).
62 63 64 1
2
3
4
5
1
2
3
4
...
64
1
2
CLK
SI
V(AO)
Pix62 Pix63 Pix64 Pix1
Pix2
Pix3
Pix4
Pix5 Pix1
Pix2
Pix3
Pix4
... Pix64
Pix1
SNH
SNH64
NRCI
Figure 5: Restarting a readout cycle
With more than 64 clock pulses until the next SI signal, put voltage tracks the voltage of the pixel 1 integration
pixel 1 is output without entering hold mode; the out- capacitor.