IC-LF1401 Datasheet, PDF (5/10 Pages) List of Unclassifed Manufacturers – 128x1 Linear Image Sensor

iC-LF1401
128x1 LINEAR IMAGE SENSOR
Rev B1, Page 5/10
ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC = VDD = 5 V ±10 %, RSET = GND, Tj = -25...85 °C unless otherwise noted
Item Symbol Parameter
No.
Conditions
Total Device
001 VDD
Digital Supply Voltage Range
002 VCC
Analog Supply Voltage Range
003 I(VDD) Supply Current in VDD
f(CLK) = 1 MHz
004 I(VCC) Supply Current in VCC
005 Vc()hi
Clamp Voltage hi at SI, CLK,DIS, Vc()hi = V() − V(VCC); I() = 1 mA
TP, RSET
006 Vc()lo
Clamp Voltage lo at SI, CLK,DIS, Vc()hi = V() − V(AGND); I() = -1 mA
TP, RSET
007 Vc()hi
Clamp Voltage hi at AO
Vc()hi = V(AO) − V(VCC); I(AO) = 1 mA
008 Vc()lo
Clamp Voltage lo at AO, VCC,
VDD, GND
Vc()lo = V() − V(AGND); I() = -1 mA
Photodiode Array
201 A()
Radiant Sensitive Area
200 µm x 56.40 µm per Pixel
202 S(λ )max Spectral Sensitivity
λ = 680 nm
203 λ ar
Spectral Application Range
S(λ ar) = 0.25 x S(λ )max
Analogue Output AO
301 Vs()lo
Saturation Voltage lo
I() = 1 mA
302 Vs()hi
Saturation Voltage hi
Vs()hi = VCC − V(), I() = -1 mA
303 K
304 V0()
Sensitivity
Offset Voltage
λ = 680 nm, package OLGA LF2C
integration time 1 ms, no illumination
305 ∆V0()
Offset Voltage Deviation during ∆V0() = V(AO)t1 − V(AO)t2,
integration mode
∆t = t2 − t1 = 1 ms
306 ∆V()
Signal Deviation during hold
mode
∆V() = V(AO)t1 − V(AO)t2,
∆t = t2 − t1 = 1 ms
307 tp(CLK-
AO)
Settling Time
Cl(AO) = 10 pF,
CLK lo → hi until V(AO) = 0.98 x V(VCC)
308 PRNU
Pixel Response Nonuniformity V(AO) = 2 V
309 INL
Integral Nonlinearity
V(AO) = 1...3.5 V
310 V_noise(AO) Output Noise Voltage
311 DR
Dynamic Range^†
Power-On Reset
V(AO) = 2 V
V(AO)_max = 3.5 V
801 VCCon Power-On Release by VCC
802 VCCoff Power-Down Reset by VCC
803 VCChys Hysteresis
VCChys = VCCon − VCCoff
Bias Current Adjust RSET
901 Ibias()
Permissible External Bias Current
902 Vref
Reference Voltage
I(RSET) = Ibias
Input Interface SI, CLK, DIS
B01 Vt()hi
Threshold Voltage hi
see Fig. 2
B02 Vt()lo
Threshold Voltage lo
see Fig. 2
B03 Vt()hys Hysteresis
Vt()hys = Vt()hi − Vt()lo, see Fig. 2
B04 I()
Pull-Down Current
B05 fclk
Permissible Clock Frequency
Min.
4.5
4.5
0.3
-1.5
0.3
-1.5
400
-250
-150
1
0.4
20
2.5
1.4
0.9
300
10
Typ. Max.
5.5
5.5
200 300
8
13
1.8
-0.3
1.5
-0.3
0.01128
0.5
980
0.5
1
2.88
400 800
50
150
200
±5^∗
±1
2
62
4.4
1
2
100
3
3.5
1.8
1.2
800
30
50
5
Unit
V
V
µA
mA
V
V
V
V
mm²
A/W
nm
V
V
V/pWs
mV
mV
mV
ns
%
%
mV_RMS
dB
V
V
V
µA
V
V
V
mV
µA
MHz
∗ _{Projected values by sample characterization}
†
DR
=
20
×
log
V (AO)max −V 0(AO)max
V_noise (AO)