IC-PNH Datasheet, PDF (3/10 Pages) IC-Haus GmbH – PHASED ARRAY NONIUS ENCODERS

iC-PNH Series
preliminary
PHASED ARRAY NONIUS ENCODERS
PACKAGING INFORMATION
Rev C4, Page 3/10
PAD LAYOUT
PAD FUNCTIONS
No. Name Function
Chip layout example.
Grey sections represent sensor layout
areas; fill factors vary.
PIN CONFIGURATION
oQFN32-5x5 (5 mm x 5 mm)
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
PIN FUNCTIONS
No. Name Function
1 VCC +4.1..5.5 V Supply Voltage
2 VREF Reference Voltage Output
3 PS_N N-Track Sine +
4 NS_N N-Track Sine -
5 PS_M M-Track Sine +
6 NS_M M-Track Sine -
7 PS_S S-Track Sine +
8 NS_S S-Track Sine -
9..16 n.c.¹⁾
17 NC_S S-Track Cosine -
18 PC_S S-Track Cosine +
19 NC_M M-Track Cosine -
20 PC_M M-Track Cosine +
21 NC_N N-Track Cosine -
22 PC_N N-Track Cosine +
23 MTB Digital Output B
24 GND Ground
25 MTA Digital Output A
26..31 n.c.¹⁾
32 VB ²⁾ +1.8..5.5 V Auxiliary Supply Voltage
BP ³⁾ Backside paddle
IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes);
1) Pin numbers marked n.c. are not connected.
2) If there is no auxiliary supply available, connect pin 32 either to VCC or GND (for chip release Y).
For chip release Z1, do not wire pin 32 or connect pin 32 to GND.
3) Connecting the backside paddle is recommended by a single link to GND. A current flow across the paddle is not permissible.