IC-NQL_11 Datasheet, PDF (19/24 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH SSI INTERFACE

iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
SSI INTERFACE
Rev D2, Page 19/24
After each communication cycle the SSI interface re-
turns to its idle state when the monoflop timeout t_tos
has elapsed. This temporal condition also determines
up to which clock line pause duration the iC-NQL re-
tains the current data output cycle - the master may
thus not undershoot a minimum clock frequency of
f(CLK)min.
Signal Names
Name
Description
S
Sensor data (S0 is LSB)
E
Error messages
Stop
Low signal
Table 32: Signal Names
CFGTOS
Code
0x00
0x01
0x02
0x03
Adr 0x06, Bit 5:4
Timeout t_tos
Ref. clock
counts
Design iC-NQL_X3:
typ. 128 µs
256-259
typ. 16 µs
32-35
typ. 4 µs
8-11
typ. 1 µs
2-5
f(CLK) min*
11 kHz
88 kHz
352 kHz
1.41 MHz
0x00
0x01
0x02
0x03
Notes
Design iC-NQL_3:
typ. 20 µs
46-46
50 kHz
typ. 20 µs
46-47
50 kHz
typ. 1.5 µs
3-4
660 kHz
typ. 1.5 µs
3-4
660 MHz
A
ref.
clock
count
is
equal
to
32
fosc
(see
El.
Char.,
A01).
The permissible max. clock frequency is specified
by E05.
*) A low clock frequency can reduce the permissible
maximum input frequency since conversion is
paused after the first falling edge on CLK for a half
clock cycle.
Table 31: Monoflop Time (SSI Timeout)
The angle conversion is halted for a half clock cycle as
soon as the interface receives the first falling edge on
CLK, what is the trigger signal to output updated posi-
tion data. The halt duration must be taken into consid-
eration when calculating the maximum input frequency.
CFGSSI
Code
0x00
0x01
0x02
0x03
Adr 0x03, Bit 7:6
Additional bits
E1, E0, zero bit
none
not permissible
none
Ring register operation
no
no
yes
Table 33: SSI Output Options
CLK
DATA
S12
MSB
Latch
Cycle
S0 Stop S12
LSB
MSB
S0 Stop
LSB
Timeout
The iC-NQL position data output contains the angle
value (S) with a bit length of 2 to 13 bits (depending
on SELRES), and up to 3 add-on bits (error messages
E1 and E0 plus a zero bit). Generally, the data output
is in binary format starting with the MSB.
Figure 15: SSI output format during ring register
operation. The example displays the
transmission of a 13-bit angle value; er-
ror messages are switched off herein
(SELRES = 0x03, CFGSSI = 0x03)
SSI Output Formats
Res Mode Error CRC T1 T2 T3 T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25
10 bit SSI X
-
S9 S8 S7 S6 ... S0 E1 E0 0 Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
Example
0000000000000
13 bit SSI -
-
S12 S11 S10 S9 ... S3 S2 S1 S0 Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
*1
SSI-R -
*2
Example
000000000000
-
S12 S11 S10 S9 ... S3 S2 S1 S0 Stop S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2
Example
0
Configuration CFGSSI = 0x00; *1) CFGSSI = 0x01; *2) CFGSSI = 0x03
Legend SSI = SSI protocol, SSI-R = SSI ring register operation
Table 34: SSI Output Formats