IC-MG Datasheet, PDF (16/20 Pages) IC-Haus GmbH – 8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MG
preliminary
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
SIGNAL LEVEL CONTROLLER
Rev C1, Page 16/20
Via the controlled power supply (pin PWR) the input
signal levels for the sine-to-digital converter can be
kept constant regardless of temperature and aging ef-
fects by tracking the sensor supply. Alternatively, the
PWR output can be used as a constant current source
for adjusting the signal conditioning, for example.
ADJ(6:0) selects the desired current for the PWR out-
put; when adjusting the signal conditioning ideally am-
plitudes of ca. 1 Vpp should be possible for the PCHx
to NCHx signal.
ADJ (8:7)
Code
00
01
10
11
Adr 0x10, bit 7:6
Function
Control to sine/cosine square
Control to sum of sine/cosine
Current source
Not permitted
Table 23: PWR Output Operating Mode
ADJ (4:0)
Code
0x00
...
0x1F
Note
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Function
3.125 % of Isc(PWR)
...
100 % of Isc(PWR)
Settings apply with current source mode.
Table 25: PWR Output Short-Circuit Current
ADJ (4:0)
Code
0x00
...
0x1A
...
0x1F
Note
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Function
60%
...
ca. 100%
...
120%
Settings apply with s/c square control mode.
Recommended entry for 1.0 V is 0x1A.
Table 26: PWR Output Signal Adjustment
ADJ (6:5)
Code
00
01
10
11
Adr 0x10, bit 5:4
Function
5 mA range
10 mA range
25 mA range
50 mA range
Table 24: PWR Output Current Source Range
ADJ (4:0)
Code
0x00
...
0x1F
Note
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Function
VDCS + VDCC = 224 mV
...
VDCS + VDCC = 472 mV
Settings apply with sum control mode.
Table 27: PWR Output Signal Adjustment
SINE-TO-DIGITAL CONVERSION
SELRES
Code
0x00E0
0x01B0
0x0398
0x0414
0x090a
0x1305
0x1804
0x3102
Adr 0x1C, bit 6:0; Adr 0x1B, bit 7:0
Angle Steps
(per period)
Interpolation
Factor
Permiss. Input
Frequency
4
x1
200 kHz
8
x2
200 kHz
16
x4
200 kHz
20
x5
200 kHz
40
x10
100 kHz
80
x20
50 kHz
100
x25
40 kHz
200
x50
20 kHz
Table 28: Resolution of Sine-to-Digital Conversion
SELHYS
Code
0x0 to 0x1
0x2
0x3 to 0xD
0xE
0xF*
Note
Adr 0x1D, bit 3:0
Function
Device test only
1 increment (≈ 1.8°)
1.5 to 6.5 increments (≈ 2.7°-11.7°)
SELRES(6:1) increments, i.e. 0.5 LSB
SELRES(6:0) increments, i.e. 1 LSB
*Not permitted in combination with
SELRES=0x00E0
Table 29: Encoding of conversion hysteresis
The angle hysteresis is set via SELHYS in multiples
of the increment size. With reference to the input sine
cycle the maximum length can be 45°.