IC-LV Datasheet, PDF (11/12 Pages) IC-Haus GmbH – 5-BIT OPTO ENCODER

iC-LV
5-BIT OPTO ENCODER
Rev A3, Page 11/12
APPLICATIONS INFORMATION
If a stable SSI output level is required all MSBs used
in the synchronization chain must be switched to the
relevant outputs on the first falling edge. The iC-LV
chain should also be synchronized in its entirety be-
fore the first rising edge of SCLK.
To guarantee functionality it is sufficient for synchroni-
zation to be completed by the second falling edge of
SCLK; SOUT is, however, then not stable for half a
clock cycle. Despite this limitation it is also possible to
synchronize with MSBs which are only output on the
first rising SCLK edge (e.g. from external SSI-com-
patible devices).
Figure 3 gives signal patterns for a cascade of three
iC-LVs.
In the synchronization modes all of the information is
output after just 4 rising clock edges per chained iC-
LV.
In keeping with the required SSI clock frequency the
time span of the internal monoflop, used to detect idle
times on the clock line, can be adjusted by externally
connecting pin RC to an RC network. Should pin RC
remain unconnected, tmf (Electrical Characteristics
No. 603) is taken as the internal time span.
Note: iC-LV stores input data received at SERIN on
the falling edge of SCLK and outputs data via SOUT
on the rising edge of SCLK.
Figure 3: SOUT in the various modes of operation.
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