HY5DU12822DT-D43 Datasheet, PDF (9/29 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

1HY5DU12822D(L)TP
HY5DU121622D(L)TP
Note :
1. UDM, LDM states are Don’t Care. Refer to below Write Mask Truth Table.(note 6)
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before
entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from
Prechagre command.
3. If a Read with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
to activate bank until CK(n+BL/2+tRP).
4. If a Write with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
to activate bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery
Time(tWR) is needed to guarantee that the last data have been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
6. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
V_IHmin ~ V_ILmax
WRITE MASK TRUTH TABLE
Function
Data Write
Data-In Mask
CKEn-1 CKEn
H
X
H
X
/CS, /RAS,
/CAS, /WE
X
X
DM
ADDR
A10/
AP
BA
Note
L
X
1,2
H
X
1,2
Note :
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.
In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
2. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
V_IHmin ~ V_ILmax
Rev. 1.0 / May 2007
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