HMT312S6DFR6C Datasheet, PDF (9/47 Pages) Hynix Semiconductor – DDR3 SDRAM Unbuffered SODIMMs Based on 2Gb D-die

Functional Block Diagram
1GB, 128Mx64 Module(1Rank of x16)
DQS0
DQS0
DM0
DQ [0:7]
DQS1
DQS1
DM1
DQ [8:15]
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
240ohm
+/-1%
ZQ
D0
DQS2
DQS2
DM2
DQ [16:23]
DQS3
DQS3
DM3
DQ [24:31]
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
240ohm
+/-1%
ZQ
D1
DQS4
DQS4
DM4
DQ [32:39]
DQS5
DQS5
DM5
DQ [40:47]
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
240ohm
+/-1%
ZQ
D2
DQS6
DQS6
DM6
DQ [48:55]
DQS7
DQS7
DM7
DQ [56:63]
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
240ohm
+/-1%
ZQ
D3
Vtt
VDD
SCL
SA0
SA1
SCL
A0
A1
Te(wmipthSSePnDso)r
A2
EVENT
EVENT
SCL
SCL
SA0
A0
(SPD)
SA1
A1
A2
WP
SDA
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
SDA
V_tt
VDDSPD
VREFCA
VREFDQ
VDD
VSS
CK0
CK0
CK1
CK1
ODT1
S1
EVENT
RESET
V_tt
SPD/TS
D0–D3
D0–D3
D0–D3
D0–D3, SPD, Temp sensor
D0–D3
D0–D3
Terminated at near
card edge
NC
NC
Temp Sensor
D0-D3
D0
D1
D2
D3
Address and Control Lines
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS relation-
ships are maintained as shown
Rank 0
Vtt
Rev. 1.1 / Sep. 2012
9