H5TQ1G43AFP Datasheet, PDF (9/77 Pages) Hynix Semiconductor – 1Gb DDR3 SDRAM

H5TQ1G43AFP(R)-xxC
H5TQ1G83AFP(R)-xxC
H5TQ1G63AFP(R)-xxC
1.3 ROW AND COLUMN ADDRESS TABLE
1Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size ¹
256Mb x 4
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9,A11
1 KB
2Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size ¹
512Mb x 4
8
BA0 - BA2
A10/AP
A12/BC
A0 - A14
A0 - A9,A11
1 KB
4Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size ¹
1Gb x 4
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9,A11
1 KB
128Mb x 8
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9
1 KB
256Mb x 8
8
BA0 - BA2
A10/AP
A12/BC
A0 - A14
A0 - A9
1 KB
512Mb x 8
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9
1 KB
64Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A12
A0 - A9
2 KB
128Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9
2 KB
256Mb x 16
8
BA0 - BA2
A10/AP
A12/BC
A0 - A14
A0 - A9
2 KB
8Gb
Configuration
2Gb x 4
1Gb x 8
512Mb x 16
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size ¹
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9, A11, A13
2 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9, A11
2 KB
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9
2 KB
Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 ^COLBITS * ORG ÷ 8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Rev. 0.4 /January 2009



































































































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