H5TC8G43MMR Datasheet, PDF (9/32 Pages) Hynix Semiconductor – 8Gb DDR3L SDRAM

ROW AND COLUMN ADDRESS TABLE
4Gb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size ¹
2Gb x 4
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9,A11
1 KB
1Gb x 8
8
BA0 - BA2
A10/AP
A12/BC
A0 - A15
A0 - A9
1 KB
Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers 
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 ^COLBITS * ORG  8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Rev. 1.1 / Apr. 2013
9