HYMD564G726A8M-M Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Low Profile Registered DDR SDRAM DIMM

HYMD564G726A(L)8M-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
-M
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle ; address and control inputs
changing once per clock cycle
1170
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst Length
=2; tRC=tRC(min); tCK=tCK(min); address and
1440
control inputs changing once per clock cycle
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=
tCK(min)
Idle Standby Current
IDD2N
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and
DM
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once per
clock cycle. VIN=VREF for DQ, DQS and DM
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref
for DQ, DQS and DM
Active Power Down
Standby Current
One bank active ; Power down mode; CKE=Low,
IDD3P _tCK=tCK(min)
Active Standby
Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM, and DQS inputs
changing twice per clock cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to the
IDD7 _{following page for detailed test condition}
Random Read
Current
IDD7A
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
tRCD=3, IOUT=0 mA, 100% DQ, DM and DQS
inputs changing twice per clock cycle; 100%
addresses changing once per clock cycle
Speed
-K -H
1080
1350
90
315
315
225
108
360
1890
1890
2340
45
22.5
3420
3420
Unit Note
-L
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.1/Jan. 2003
8