HYMD564G726A8-M Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD564G726A(L)8-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
Parameter Symbol
Test Condition
Speed
-M -K -H
Unit Note
-L
Operating Current
One bank; Active - Precharge ; tRC=tRC(min); tCK=
IDD0
tCK(min) ; DQ,DM and DQS inputs changing twice
per clock cycle ; address and control inputs changing
1170
1080
1080
1080
mA
once per clock cycle
Operating Current
One bank ; Active - Read - Precharge ; Burst Length
IDD1 = 2 ; tRC=tRC(min); tCK= tCK(min) ; address and 1440 1350 1350 1350 mA
control inputs changing once per clock cycle
Precharge Power
Down Standby
Current
IDD2P
All banks idle ; Power down mode ; CKE= Low, tCK=
tCK(min)
90
90
90
90 mA
Idle Standby Current IDD2N Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
315
mA
/CS = High, All banks idle ; tCK= tCK(min) ; CKE =
Idle Standby Current IDD2F High ; address and control inputs changing once per
315
mA
clock cycle. VIN = VREF for DQ, DQS and DM
Idle Quiet Standby
Current
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
IDD2Q Addresses and other control inputs stable, Vin=Vref
for DQ, DQS and DM
225
mA
Active Power Down
Standby Current
IDD3P
One bank active ; Power down mode ; CKE= Low,
tCK= tCK(min)
108
mA
/CS= HIGH; CKE = HIGH; One bank; Active-
Active Standby
Current
Precharge; tRC = tRAS(max); tCK = t CK (max); DQ,
IDD3N DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
360
mA
clock cycle
Operating Current
Burst = 2 ; Reads; Continuous burst; One bank
IDD4R active; Address and control inputs changing once per
clock cycle; tCK= tCK (min); IOUT = 0mA
1890
Burst = 2; Writes; Continuous burst; One bank active;
Operating Current
IDD4W
Address and control inputs changing once per clock
cycle; tCK = tCK (min); DQ, DM, and DQS inputs
1890
mA
changing twice per clock cycle
Auto Refresh Current
IDD5
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
2340
Self Refresh Current
IDD6
CKE =< 0.2V; External clock on; tCK
= tCK(min)
Normal
Low Power
45
mA
22.5
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
3420
mA
4banks active read with activate every 20ns, AP(Auto
Random Read
Current
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
IDD7A mA, 100% DQ, DM and DQS inputs changing twice
per clock cycle; 100% addresses changing once per
3420
mA
clock cycle
Rev. 0.1/Jan. 2003
8