HYMD264726C8-M Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD264726C(L)8-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
Operating Current
IDD0
One bank; Active Precharge; tRC=tRC(min);
tCK= tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
control inputs changing once per clock cycle
1485 1305 1305 1260 mA
Operating Current
IDD1
One bank; Active-Read-Precharge; Burst
Length =2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
clock cycle
1890 1620 1620 1530 mA
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
360
mA
Idle Standby Current
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
IDD2F _{per clock cycle. VIN=VREF for DQ, DQS and}
900 720 720 630 mA
DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
450
mA
Active Standby Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK (min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
1080 900 900 900 mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
3150 2700 2700 2160
Operating Current
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM,
3150 2700 2700 2160 ^mA
and DQS inputs changing twice per clock cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
2610
2340
2340
2205
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK =tCK(min)
Normal
Low Power
54
27
mA
mA
Operating Current - Four
Bank Operation
IDD7
Four bank interleaving with B=4 Refer to the
following page for detailed test condition
3375 3195 3195 2970 mA
Rev. 0.1 / Mar. 2003
8