HYMD232G726A8M-M Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Low Profile Registered DDR SDRAM DIMM

HYMD232G726A(L)8M-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
Operating Current
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
1595 1505 1505 1460 mA
control inputs changing once per clock cycle
Operating Current
One bank; Active - Read - Precharge; Burst
IDD1
Length =2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
2000 1820 1820 1730
mA
clock cycle
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
830
mA
Idle Standby Current
/CS=High, All banks idle; tCK=tCK(min);
IDD2F
CKE=High
; address and control inputs changing once per
1100
1010
1010
965
mA
clock cycle. VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
875
mA
Active Standby Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
1190 1100 1100 1100 mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
3260 2900 2900 2360
Operating Current
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM,
3260 2900 2900 2360 ^mA
and DQS inputs changing twice per clock cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
2420
2240
2240
2105
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK =tCK(min)
Normal
Low Power
377
363.5
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
3485 3395 3395 3170
mA
Rev. 0.2/May. 02
8