HYMD232646B8-M Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD232646B(L)8-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
Operating Current
One bank; Active Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs
IDD0 _{changing twice per clock cycle; address and} 840 760 760 720 mA
control inputs changing once per clock cycle
Operating Current
One bank; Active - Read Precharge; Burst
Length =2; tRC=tRC(min); tCK=tCK(min);
IDD1 _{address and control inputs changing once per} 1200 1040 1040 960 mA
clock cycle
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
160
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle ; tCK=tCK(min);
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF
for DQ, DQS and DM
400 320 320 280 mA
Active Power Down
Standby Current
One bank active; Power down mode;
IDD3P _{CKE=Low, tCK=tCK(min)}
200
mA
Active Standby
Current
/CS=HIGH; CKE=HIGH; One bank; Active
Precharge; tRC=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per 480 400 400 400 mA
clock cycle; Address and other control inputs
changing once per clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
2320
2000
2000
1520
Operating Current
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
IDD4W once per clock cycle; tCK=tCK(min); DQ, DM, 2320 2000 2000 1520 ^mA
and DQS inputs changing twice per clock
cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B
at 133Mhz; distributed refresh
1840 1680 1680 1560
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; ^Normal
tCK=tCK(min)
Low Power
24
12
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
2520
2440
2440
2240
mA
Rev. 0.2/Dec. 02
8