HYMD2326468-K Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD232646(L)8-K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Operating Current
Operating Current
Precharge Power Down
Standby Current
Idle Standby Current
Active Power Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current - Four
Bank Operation
Symbol
Test Condition
Speed
-K -H -L
Unit Note
One bank; Active Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
IDD0 _{twice per clock cycle; address and control inputs} 760 760 720 mA
changing once per clock cycle
One bank; Active - Read Precharge; Burst Length
IDD1 =2; tRC=tRC(min); tCK=tCK(min); address and
960 960 880 mA
control inputs changing once per clock cycle
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
160 160 120 mA
/CS=High, All banks idle ; tCK=tCK(min); CKE=
IDD2F High; address and control inputs changing once
320
mA
per clock cycle. VIN=VREF for DQ, DQS and DM
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
200
200
160
mA
/CS=HIGH; CKE=HIGH; One bank; Active
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
IDD3N DM and DQS inputs changing twice per clock
400
mA
cycle; Address and other control inputs changing
once per clock cycle
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
1640
1640
1280
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
IDD4W _{per clock cycle; tCK=tCK(min); DQ, DM, and DQS} 1840 1840 1520 mA
inputs changing twice per clock cycle
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
1680 1680 1560
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
Low Power
24
12
mA
mA
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
2440 2440 2240 mA
Rev. 0.7/Oct. 02
8