HYMD216646C6J-J Datasheet, PDF (8/18 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD216646C6J-D4/D43/J
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
D43 D4 -J
One bank; Active Precharge; tRC=tRC(min);
Operating Current
tCK=tCK(min); DQ,DM and DQS inputs changing
IDD0 _{twice per clock cycle; address and control inputs}
TBD
420
changing once per clock cycle
One bank; Active - Read Precharge; Burst Length
Operating Current
IDD1 =2; tRC=tRC(min); tCK=tCK(min); address and
TBD
600
control inputs changing once per clock cycle
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
TBD
80
/CS=High, All banks idle ; tCK=tCK(min); CKE=
Idle Standby Current IDD2F High; address and control inputs changing once
TBD
200
per clock cycle. VIN=VREF for DQ, DQS and DM
Active Power Down
One bank active; Power down mode; CKE=Low,
Standby Current
IDD3P _tCK=tCK(min)
TBD
100
Active Standby
Current
/CS=HIGH; CKE=HIGH; One bank; Active
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
IDD3N DM and DQS inputs changing twice per clock
TBD
240
cycle; Address and other control inputs changing
once per clock cycle
Burst=2; Reads; Continuous burst; One bank
Operating Current
IDD4R active; Address and control inputs changing once
TBD
1160
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
Operating Current
IDD4W
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM, and DQS
TBD
inputs changing twice per clock cycle
1160
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
TBD
920
Self Refresh Current
CKE=<0.2V; External clock on;
IDD6 _tCK=tCK(min)
Normal
Low Power
TBD
TBD
12
6
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
TBD
1340
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.3 / Aug. 2003
8