HYMD132G725EL4-M Datasheet, PDF (8/17 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD132G725E(L)4-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS=0V)
Parameter
Operating Current
Operating Current
Precharge Power Down
Standby Current
Idle Standby Current
Active Power Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current - Four
Bank Operation
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
TBD
TBD
TBD
TBD
mA
changing once per clock cycle
IDD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
TBD TBD TBD TBD
mA
clock cycle
IDD2P
All banks idle; Power down mode ; CKE=Low,
tCK=tCK(min)
TBD TBD TBD TBD mA
/CS=High, All banks idle; tCK=tCK(min);
IDD2F
CKE=High; address and control inputs changing
once per clock cycle.
TBD TBD TBD TBD
mA
VIN=VREF for DQ, DQS and DM
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
TBD
TBD
TBD
TBD
mA
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
IDD3N DM and DQS inputs changing twice per clock
TBD TBD TBD TBD mA
cycle; Address and other control inputs changing
once per clock cycle
Burst=2; Reads; Continuous burst; One bank
IDD4R active; Address and control inputs changing once TBD TBD TBD TBD mA
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
TBD
TBD
TBD
TBD
mA
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
IDD5 10*tCK for DDR266A & DDR266B at 133Mhz;
TBD TBD TBD TBD mA
distributed refresh
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal TBD TBD TBD TBD mA
Low Power TBD TBD TBD TBD mA
IDD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
TBD TBD TBD TBD mA
Rev. 0.1 / Sep. 2003
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