HYMD116725B8J-J Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD116725B(L)8J-J
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS=0V)
Parameter
Symbol
Test Condition
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst Length= 2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode ; CKE=Low,
tCK=tCK(min)
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once
per clock cycle.
VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
Active Standby Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed
refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
Low Power
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
Speed
-J
810
990
180
360
180
360
2070
2070
1440
18
9
2700
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.2/Jun. 02
8