HY62U8400A Datasheet, PDF (8/11 Pages) Hynix Semiconductor – 512Kx8bit CMOS SRAM

HY62U8400A Series
Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
DATA RETENTION ELECTRIC CHARATERISTIC
TA = 0¡ Éto 70¡ É(Normal)/-25°C to 85°C (Extended) /-40°C to 85°C (Industrial), unless otherwise specified.
Symbol
Parameter
Test Condition
Min Typ Max Unit
VDR
Vcc for Data Retention
/CS > Vcc-0.2V,
2.0
-
-
V
VIN > Vcc-0.2V or VIN < 0.2V
ICCDR Data Retention Current
Vcc = 3.0V,
LL
-
-
20 uA
/CS>Vcc-0.2V,
LL-E
-
-
30 uA
VIN>Vcc-0.2V or VIN<0.2V
LL-I
-
-
30 uA
tCDR Chip Deselect to Data
0
-
-
ns
Retention Time
tR
Operating Recovery Time
tRC(2) -
-
ns
Notes:
1. Typical values are at the condition of TA = 25°C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC
2.7V
DATA RETENTION MODE
tCDR
tR
2.2V
VDR
/CS
VSS
/CS > VCC-0.2V
Rev 07 / Apr. 2001
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