HY57V641620HG Datasheet, PDF (7/12 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

A C C H A R A C T E R IS T IC S I ( A C o p e r a t i n g c o n d i t i o n s u n l e s s o t h e r w i s e n o t e d )
HY57V641620HG
Parameter
Symbol
-5
M in M a x
-55
-6
M i n M a x M in M a x
-7
Min M a x
-K
-H
M in M a x M in M a x
-8
M in M a x
-P
M in M a x
-S
Min M a x
Unit Note
System clock
cycle time
CAS Latency =
tCK3
3
CAS Latency =
tCK2
2
55
55
6
7
7.5
7.5
8
10
10
ns
1000
1000
100
0
1000
1000
1000
1000
1000
1000
10
10
10
10
7.5
10
10
10
12
ns
Clock high pulse width
tCHW
2.5
- 2.75 -
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
2.5
- 2.75 -
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Access time
from clock
CAS Latency =
tAC3
3
CAS Latency =
tAC2
2
-
5.4
-
5.4
-
5.4
-
5.4
-
5.4
-
6
-
6
-
6
-
6
-
5.4
5.4
-
6
6
-
6
ns
2
6
-
6
-
6
-
8
ns
Data-out hold time
tOH
2.5
-
2.5
-
2.7
-
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address hold time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE hold time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command hold time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time tOLZ
1
-
1
-
1
-
1.5
-
1.5
-
1.5
-
1
-
1
-
2
-
ns
CLK to data
CAS Latency =
tOHZ3
3
3
6
ns
output in high
5.4
5.4
5.4
5.4
5.4
5.4
6
6
Z-time
CAS Latency =
tOHZ2
2
3
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.5/Jun.01
7