HM6C5332 Datasheet, PDF (7/10 Pages) Hynix Semiconductor – HM6C5332 - 1.2GHz/250MHz Dual Frequency Synthesizer

PRELIMINARY
Programmable Modes
Several modes of operation can be programmed with bits R16-R18 including the phase detector polarity and charge pump
High Z State. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes and
truth table for the programmable modes are shown below.
C1
C2
R16
R17
R18
R19
R20
0
0 IF Phase Detector Polarity
IF I_CPO
0
1 RF Phase Detector Polarity
RF I_CPO
1
0
-
-
1
1
-
-
IF D_O High Z
RF D_O High Z
-
-
IF LD
RF LD
IF Prescaler
RF Prescaler
IF F_O
RF F_O
Powerdown IF
Powerdown RF
Mode Select Truth Table
PHASE DETECTOR
POLARITY
D_O High Z STATE
I_CPO
(NOTE 1)
IF PRESCALER
RF
PRESCALER
POWERDOWN
(NOTE 2)
0
Negative
Normal Operation LOW
8/9
64/65
Powered Up
1
Positive
High Z State
HIGH
16/17
128/129
Powered Down
NOTES:
1. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and
debiasing of its respective f_IN inputs (to a high impedance state). Powerdown forces the respective charge pump and
phase comparator logic to a High Z State condition. The R counter functionality does not become disabled until both IF
and RF powerdown bits are activated. The OSC_IN pin reverts to a high impedance state when this condition exists. The
control register remains active and capable of loading and latching in data during all the powerdown modes.
F_O LD (Pin 10) Output Truth Table
RF R[19]
(RF LD)
IF R[19]
(IF LD)
RF R[20]
(RF F_O)
IF R[20]
(IF F_O)
F_O OUTPUT STATE
0
0
0
0
Disabled (Note1)
0
1
0
0
IF Lock Detect (Note2)
1
0
0
0
RF Lock Detect (Note2)
1
1
0
0
RF/IF Lock Detect (Note2)
X
0
0
1
IF Reference Divider Output
X
0
1
0
RF Reference Divider Output
X
1
0
1
IF Programmable Divider Output
X
1
1
0
RF Programmable Divider Output
0
0
1
1
For Internal Use Only
0
1
1
1
For Internal Use Only
1
0
1
1
For Internal Use Only
1
1
1
1
Counter Reset (Note4)
X = don’t care condition
NOTES:
1. When the F_O LD output is disabled, it is actively pulled to a low logic state.
2. Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is
selected, the pins output is HIGH, with narrow pulse LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and
IF are both locked.
3. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes
counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R
counter is also forced to Reset, allowing smooth acquisition upon powering up.