H55S5122DFR-60M Datasheet, PDF (7/54 Pages) Hynix Semiconductor – 512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O

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512Mbit (16Mx32bit) Mobile SDR Memory
H55S5122DFR Series / H55S5132DFR Series
BALL DESCRIPTION
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A13
RAS, CAS, WE
DQM0 ~ DQM3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
TYPE
DESCRIPTION
INPUT
Clock: The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
INPUT
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
INPUT Chip Select: Enables or disables all inputs except CLK, CKE, DQM0~DQM3
INPUT
Bank Address: Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
INPUT
For 1KBytes Page Size, Row Address: RA0 ~ RA13, Column Address: CA0 ~ CA7
For 2KBytes Page Size, Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
INPUT
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
INPUT
Data Mask: Controls output buffers in read mode and masks input data in write
mode
I/O
Data Input/Output: Multiplexed data input/output pin
SUPPLY Power supply for internal circuits
SUPPLY Power supply for output buffers
-
No connection
Rev 1.5 / Jan. 2009
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