HV7151SP Datasheet, PDF (65/89 Pages) Hynix Semiconductor – CMOS Image Sensor with Image Signal Processing

Confidential
HV7151SP
CMOS Image Sensor
With Image Signal Processing
5. 5x5 Color Interpolation Timing (CifMode)
5x5 Color Interpolation Frame Timing Related Parameters
Master Clock Frequency(MCF)
19.2 Mhz
PLL Out Clock Frequency(PCF) MCF*2 = 38.4Mhz
Divided Clock Frequency(DCF) PCF/1 = 38.4Mhz Sensor Clock Frequency(SCF) DCF/2 = 19.2Mhz
Sensor Clock Period(SCP) 1/19.2Mhz = 52ns
Window Width
352
Window Height
288
HBLANK Value
208
VBLANK Value
8
VSYNC Mode
Line Mode
Line Clock Period(LCP)
1366 SCPs
Output Bus Width
8bit
VGA Video Output Frequency
Irregular clock
Final Video Output Size
352x288
IDLE SLOT(4LCPs + (1024+HBLANK)*4)
Core Frame
Time
HBLANK
(208 SCPs)
HSYNC (1152 SCPs)
Active Data: 352 EA
LCP(1366 SCPs)
ISP Dummy
(6 SCPs)
Video Lines is
active every
LCP, that is,
288 Video Lines
for 864 LCPs
HOLD SLOT
(Integration Time – Core Frame Time)
VBLANK[VSYNC]
(8 LCPs)
Real Frame
Time
If Integration Time < Core Frame Time, Real Frame Time is
4 * (208 + 1152+6) SCPs + 864 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 *
(208+1024)= 1201544 SCPs = 0.062580sec -> 15.979 frame per sec.
else Real Frame Time is
Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs.
HOLD SLOT in frame timing appears only if integration time is larger than core frame time.
QCifMode Frame rate is same as CifMode Frame rate.
This document is a general product description and is subject to change without notice. Hynix
Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent
licenses are implied.
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2003 Hynix Semiconductor Inc.