HYMD512M646DLFP8-D43 Datasheet, PDF (6/17 Pages) Hynix Semiconductor – 200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA)

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200pin DDR SDRAM SO-DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
1GB, 128M x 64 Unbuffered SO-DIMM: HYMD512M646D[L]FP8
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Test Condition
One bank; Active - Precharge; tRC=tRC(min);
DDR400B
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
1520
once per clock cycle
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
1840
inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
2160
cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs chang-
2320
ing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distrib-
2560
uted refresh
CKE=<0.2V; External clock on; tCK Normal
=tCK(min)
Low Power
Four bank interleaving with BL=4 Refer to the follow-
ing page for detailed test condition
3360
Speed
DDR333
1440
1680
160
560
720
960
2000
2160
2400
80
48
3280
DDR266B
1280
1440
1840
1920
2240
3200
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 / June 2007
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