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| HYMD264726C8J-J Datasheet, PDF (6/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM | |||
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CAPACITANCE (TA=25oC, f=100MHz )
HYMD264726C(L)8-M/K/H/L
Parameter
Pin
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE0, CKE1
CS0, CS1
Input Capacitance
Input Capacitance
Data Input / Output Capacitance
Data Input / Output Capacitance
CK0, /CK0, CK1, /CK1, CK2,/CK2
DM0 ~ DM8
DQ0 ~ DQ63, DQS0 ~ DQS8
CB0 ~ CB7
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
CIO2
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Output
VTT
RT=50â¦
Zo=50â¦
CL=30pF
VREF
Rev. 0.1 / Mar. 2003
6
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