HY5DU561622EFP Datasheet, PDF (4/29 Pages) Hynix Semiconductor – 256Mb DDR SDRAM

PIN CONFIGURATION
1
HY5DU56822E(L)FP
HY5DU561622E(L)FP
(X8)
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
7
VSS
A
VDD
DQ6
B
DQ1
DQ5
C
DQ2
DQ4
D
DQ3
DQS
E
NC
DM
F
NC
CK
G
WE
CKE
H
RAS
A9
J
BA1
A7
K
A0
A5
L
A2
VSS
M
VDD
x8 Device Ball Pattern
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
VDDQ
NC
NC
NC
NC
NC
(X16)
1
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
2
3
7
DQ15
VSS
A
VDD
DQ0
VDDQ
DQ13
B
DQ2
VSSQ
VSSQ
DQ11
C
DQ4
VDDQ
VDDQ
DQ9
D
DQ6
VSSQ
VSSQ
UDQS
E
LDQS
VDDQ
VSS
UDM
F
LDM
VDD
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
x16 Device Ball Pattern
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
: Ball Existing
: Depopulated Ball
[ For Reference Only ]
Top View (See the balls through the Package)
123456789
A
1.0mm
B
C
D
E
F
13.0mm
G
H
J
K
L
M
8.0mm
0.8mm
BGA Package Ball Pattern
Top View
ROW AND COLUMN ADDRESS TABLE
ITEMS
Organization
Row Address
Column Address
Bank Address
Auto Precharge Flag
Refresh
32Mx8
8M x 8 x 4banks
A0 - A12
A0-A9
BA0, BA1
A10
8K
16Mx16
4M x 16 x 4banks
A0 - A12
A0-A8
BA0, BA1
A10
8K
Rev. 1.1 / June 2006
4