HYMP164U64CP6-C4 Datasheet, PDF (3/29 Pages) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs

1240pin DDR2 SDRAM Unbuffered DIMMs
Input/Output Functional Description
Symbol
CK[2:0], CK[2:0]
CKE[1:0]
S[1:0]
RAS, CAS,
WE
ODT[1:0]
Vref
V_DDQ
BA[2:0]
Type Polarity
Differential
SSTL
Crossing
SSTL Active High
SSTL Active Low
SSTL Active Low
SSTL Active High
Supply
Supply
SSTL
-
Pin Description
CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are
sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read)
data is reference to the crossing of CK and /CK (Both directions of crossing)
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1
/RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immu-
nity. For all current DDR2 unbuffered DIMM designs, V_DDQ shares the same power plane
as V_DD pins.
Selects which DDR2 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, Address input difines the row
address(RA0~RA15)
A[9:0], A10/AP,
A[13:11]
DQ[63:0],
CB[7:0]
DM[8:0]
V_DD,V_SS
DQS[8:0],
DQS[8:0]
SA[2:0]
SDA
SCL
VDDSPD
SSTL
During a Read or Write command cycle, Address input defines the column address when
sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to
-
the column address, AP is used to invoke autoprecharge operation at the end of the
burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines
the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge
command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to
precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
SSTL
-
Data and Check Bit Input/Output pins.
SSTL Active High
Supply
Differential
SSTL
crossing
-
-
-
Supply
DM is an input mask signal for write data. Input data is masked when DM is sampled
High coincident with that input data during a write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. V_DD and V_DDQ
pins are tied to V_DD/V_DDQ planes on these modules.
Data strobe for input and output data. For Rawcards using x16 organized DRAMs,
DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of
the DRAM
These signals are tied at the system planar to either V_SS or V_DD to configure the serial
SPD EEPROM.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to V_DD to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to V_DD to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power
plane. EEPROM supply is operable from 1.7V to 3.6V.
Rev. 0.6 / Jul. 2008
3