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H5PS1G63JFR Datasheet, PDF (27/62 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM
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H5PS1G63JFR Series
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 * tCK or 2 * nCK) is required irrespective of operating frequency
5. Timings are specified with command/address input slew rate of 1.0 V/ns. See System Derating for other
slew rate values.
6. Timings are guaranteed with DQs, DM, and DQS’s(DQS/RDQS in singled ended mode) input slew rate of
1.0 V/ns. See System Derating for other slew rate values.
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals
with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended
mode. See System Derating for other slew rate values.
8. tDS and tDH derating
DQ
S le w
rat e
V /ns
tD S , tD H D e rat in g V alu e s fo r D D R 2 -4 00 , D D R 2 -5 33 (A L L u n it s in 'p s' , N o te 1 ap p lie s to e n tire T a b le)
DQ S , DQ S D iffe re ntia l Sle w R a te
4 .0 V /n s 3 .0 V /n s 2.0 V/n s 1 .8 V /n s 1 .6 V /n s 1.4 V/n s 1.2 V /n s 1 .0 V /n s 0 .8 V /n s
△ △ △△ △ △△ △ △△ △ △△ △△ △ △△
tD S t D H t D S t D H t D S tD H tDS tD H tD S t DH t DS tDH tD S tD H tD S t D H tD S t D H
2 .0 1 25 4 5 1 2 5 45 +12 5 +4 5 -
-
-
-
-
-
-
-
-
-
-
-
1 .5 8 3 2 1 8 3 21 +8 3 +2 1 95 3 3
-
-
-
-
-
-
-
-
-
-
1.0 0
0
0
0
0
0
12 1 2 2 4 24
-
-
-
-
-
-
-
-
0 .9
-
- - 1 1 -1 4 -1 1 - 14 1
-2 1 3 10 2 5 2 2
-
-
-
-
-
-
0 .8
-
-
-
- -2 5 - 31 -1 3 -1 9 - 1 -7 1 1
5
23 1 7
-
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-
-
0 .7
-
-
-
-
-
- -3 1 -4 2 - 19 -1 9 - 7 -8
5
-6 17
6
-
-
0 .6
-
-
-
-
-
-
-
- - 43 -5 9 -3 1 - 47 -1 9 -3 5 -7 -2 3 5 -1 1
0 .5
-
-
-
-
-
-
-
-
-
- -7 4 - 89 -6 2 -7 7 - 50 -6 5 - 3 8 -5 3
0 .4
-
-
-
-
-
-
-
-
-
-
-
- -1 2 7 -1 40 - 11 5 -1 2 8 -1 03 - 11 6
DQ
S le w
rat e
V /ns
tD S, t D H D e ra tin g V a lu es fo r D D R 2 -6 6 7, D D R 2 -8 0 0( A L L u n it s in ' p s ', N o t e 1 a pp lies to e n t ire T a b le )
D QS , D Q S D iff ere n t ia l S le w R a t e
4 .0 V /n s 3.0 V /n s 2.0 V /n s 1.8 V/n s 1.6 V/n s 1 .4 V/ns 1 .2 V /n s 1 .0 V /n s 0 .8 V /ns
△△ △△ △△ △△ △△△ △△ △△ △△ △
t DS t DH t DS t DH tD S t DH tD S t D H tD S tD H tDS tD H tDS tD H tDS tDH tD S tDH
2 .0 1 0 0 45 1 0 0 45 1 0 0 4 5
-
-
-
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-
-
-
-
-
-
-
-
1 .5 6 7 21 6 7 21 6 7 2 1 7 9 3 3
-
-
-
-
-
-
-
-
-
-
1.0 0
0
0
0
0
0
12 12 24 24
-
-
-
-
-
-
-
-
0.9 -
-
- 5 -1 4 - 5 -1 4 7
-2 1 9 1 0 31 2 2
-
-
-
-
-
-
0.8 -
-
-
- - 13 -3 1 - 1 -1 9 1 1 -7 23
5
35 1 7
-
-
-
-
0.7 -
-
-
-
-
- - 10 -4 2 2 -3 0 14 -1 8 26 - 6 38 6
-
-
0.6 -
-
-
-
-
-
-
- - 10 -5 9 2 -4 7 14 -3 5 26 - 23 3 8 - 11
0.5 -
-
-
-
-
-
-
-
-
- - 24 -8 9 -1 2 -7 7 0 - 65 1 2 - 53
0.4 -
-
-
-
-
-
-
-
-
-
-
- -5 2 -1 40 -4 0 -1 28 -2 8 - 1 16
Rev. 1.7 / Nov. 2011
27
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