HY5DU323222QP Datasheet, PDF (26/29 Pages) Hynix Semiconductor – 32M(1Mx32) DDR SDRAM

11HY5DU323222QP
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Row Address to Column Address Delay for
Read
Row Address to Column Address Delay for
Write
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Last Data-In to Precharge Delay Time
(Write Recovery Time : tWR)
Last Data-In to Read Command
Auto Precharge Write Recovery +
Precharge Time
System Clock Cycle Time
CL = 3.0
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Input Setup Time
Input Hold Time
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-In Hold Time to DQS-In (DQ & DM)
Symbol
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRRD
tCCD
tRP
tDPL
tDRL
tDAL
tCK
tCH
tCL
tAC
tDQSCK
tDQSQ
tQH
tHP
tQHS
tIS
tIH
tDQSH
tDQSL
tDQSS
tDS
tDH
5
Min
Max
60
-
70
-
40
120K
4
-
6
Unit
Min
Max
66
-
ns
72
-
ns
45
120K
ns
4
-
CK
2
-
3
-
CK
2
-
2
-
CK
1
-
1
-
CK
4
-
4
-
CK
2
-
2
-
CK
2
-
2
-
CK
6
-
6
-
CK
5
10
6
10
ns
0.45
0.55
0.45
0.55
CK
0.45
0.55
0.45
0.55
CK
-0.9
0.9
-0.9
0.9
CK
-0.7
0.7
-0.7
0.7
ns
-
0.4
-
0.4
ns
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
tCH/L
min
-
tCH/L
min
-
ns
-
0.75
-
0.75
ns
1.0
-
1.0
-
ns
1.0
-
1.0
-
ns
0.4
0.6
0.4
0.6
ns
0.4
0.6
0.4
0.6
CK
0.75
1.25
0.75
1.25
CK
0.5
-
0.5
-
CK
0.5
-
0.5
-
ns
Note
1,6
1,5
6
2
2
3
3
Rev. 0.3 / Jun. 2005
26