HMT325R7EFR8A Datasheet, PDF (26/70 Pages) Hynix Semiconductor – DDR3L SDRAM Registered DIMM Based on 2Gb E-die

AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
DDR3L-800/1066
Min
Max
DDR3L-1333/1600
Min
Max
DDR3L-1866
Min
Max
Unit Notes
VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD
V
VIL.CA(DC90) DC input logic low
VSS Vref - 0.09 VSS Vref - 0.09 VSS Vref - 0.09 V
VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 Vref + 0.160 Note2
-
-
V
VIL.CA(AC160) AC input logic low
Note2 Vref - 0.160 Note2 Vref - 0.160
-
-
V
VIH.CA(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 Vref + 0.135 Note2 V
VIL.CA(AC135) AC input logic low
Note2 Vref - 0.135 Note2 Vref - 0.135 Note2 Vref - 0.135 V
VIH.CA(AC125) AC Input logic high
-
-
-
-
Vref + 0.125 Note2
V
VIL.CA(AC125) AC input logic low
-
-
-
-
Note2 Vref - 0.125 V
V_RefCA(DC)
Reference Voltage for
ADD, CMD inputs
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
1
1
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
3,4
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 39.
3. The ac peak noise on V_Ref may not allow V_Ref to deviate from V_RefCA(DC) by more than +/-1% VDD (for refer-
ence: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single
Ended AC and DC Input Levels for DQ and DM" on page 27), the respective levels in JESD79-3 (VIH/L.CA(DC100),
VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/
L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) do not apply when
the device is operated in the 1.35 voltage range.
Rev. 1.0 / Aug. 2013
26