H5TQ4G43AFR Datasheet, PDF (23/35 Pages) Hynix Semiconductor – 4Gb DDR3 SDRAM

Table 8 - IDD4W Measurement-Loop Pattern^a)
Data^b)
00
1
2,3
4
5
6,7
1 8-15
2 16-23
3 24-31
4 32-39
5 40-47
6 48-55
7 56-63
WR 0 1 0 0 1 0 00 0 0 0 0 00000000
D 1 0 0 0 1 0 00 0 0 0 0
-
D,D 1 1 1 1 1 0 00 0 0 0 0
-
WR 0 1 0 0 1 0 00 0 0 F 0 00110011
D 1 0 0 0 1 0 00 0 0 F 0
-
D,D 1 1 1 1 1 0 00 0 0 F 0
-
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 9 - IDD5B Measurement-Loop Pattern^a)
Data^b)
00
REF 0 0 0 1 0 0 0 0 0 0 0
-
1 1.2
D, D 1 0 0 0 0 0 00 0 0 0 0
-
3,4
D, D 1 1 1 1 0 0 00 0 0 F 0
-
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Apr. 2013
23