H5MS1262EFP-J3E Datasheet, PDF (22/62 Pages) Hynix Semiconductor – 128M (8Mx16bit) Mobile DDR SDRAM

Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
DC CHARACTERISTICS
Parameter
Symbol
Test Condition
DDR
333
Max
DDR
266
DDR ^{Unit Note}
200
Operating one bank
active-precharge current
tRC = tRC(min); tCK = tCK(min); CKE is HIGH; CS is
IDD0 HIGH between valid commands; address inputs are 45 40 35 mA 1
SWITCHING; data bus inputs are STABLE
Precharge power-down
standby current
all banks idle; CKE is LOW; CS is HIGH; tCK =
IDD2P tCK(min); address and control inputs are SWITCH-
ING; data bus inputs are STABLE
0.3
mA
Precharge power-down
all banks idle; CKE is LOW; CS is HIGH; CK = LOW;
standby current
IDD2PS CK = HIGH; address and control inputs are SWITCH-
0.3
mA
with clock stop
ING; data bus inputs are STABLE
Precharge non power-down
standby current
all banks idle; CKE is HIGH; CS is HIGH, tCK =
IDD2N tCK(min); address and control inputs are SWITCH-
ING; data bus inputs are STABLE
5
mA
Precharge non power-down
all banks idle; CKE is HIGH; CS is HIGH; CK = LOW;
standby current
IDD2NS CK = HIGH; address and control inputs are SWITCH-
3
with clock stop
ING; data bus inputs are STABLE
Active power-down
standby current
Active power-down
standby current
with clock stop
one bank active; CKE is LOW; CS is HIGH; tCK =
IDD3P tCK(min); address and control inputs are SWITCH-
2
ING; data bus inputs are STABLE
mA
one bank active; CKE is LOW; CS is HIGH; CK =
IDD3PS LOW; CK = HIGH; address and control inputs are
1.2
SWITCHING; data bus inputs are STABLE
Active non power-down
standby current
one bank active; CKE is HIGH; CS is HIGH; tCK =
IDD3N tCK(min); address and control inputs are SWITCH-
ING; data bus inputs are STABLE
10
mA
Active non power-down
standby current
with clock stop
one bank active; CKE is HIGH; CS is HIGH; CK =
IDD3NS LOW; CK = HIGH; address and control inputs are
SWITCHING; data bus inputs are STABLE
8
mA
one bank active; BL=4; CL=3; tCK = tCK(min);
Operating burst read current
IDD4R
continuous read bursts; IOUT=0mA; address inputs
are SWITCHING, 50% data change each burst trans-
100
90
70 mA
fer
1
one bank active; BL=4; tCK=tCK(min); continuous
Operating burst write current IDD4W write bursts; address inputs are SWITCHING; 50% 80 70 60 mA
data change each burst transfer
tRC=tRFC(min); tCK=tCK(min); burst refresh; CKE
Auto Refresh Current
IDD5 is HIGH; address and control inputs are SWITCH-
80
mA
ING; data bus inputs are STABLE
Self Refresh Current
IDD6
CKE is LOW; CK=LOW; CK=HIGH;
Extended Mode Register set to all 0's; address and
control inputs are STABLE; data bus inputs are STA-
BLE
See Next Page
uA 2
Deep Power Down Current
IDD8 Address, control and data bus inputs are STABLE
10
uA 4
Rev 1.1 / July. 2009
22