HMT325S6CFR8A Datasheet, PDF (21/50 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered SODIMMs Based on 2Gb C-die

Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
DDR3L-800, 1066, 1333, 1600
Min
Max
V_IX
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
-150
150
V_IX
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
150
Notes:
1The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL  25mV 
VSEH - ((VDD/2) + Vix (Max))  25mV
Unit Notes
mV 1
mV 1
Slew Rate Definitions for Single-Ended Input Signals
Rev. 0.3 /Jun. 2012
21