H57V2582GTR-60C Datasheet, PDF (21/22 Pages) Hynix Semiconductor – 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O

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Synchronous DRAM Memory 256Mbit
H57V2582GTR Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
CKE
Command
Current
State
Previous Current
Cycle Cycle
CS
RAS CAS
WE
BA0,
BA1
ADDR
Action
H
Any State
other than
H
listed above
L
Refer to operations of
H
X
X
X
X
X
X the Current State
Truth Table
L
X
X
X
X
X
X
Begin Clock Suspend
next cycle
H
X
X
X
X
X
X
Exit Clock Suspend
next cycle
L
L
X
X
X
X
X
X Maintain Clock Suspend
Notes
Note :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
Rev 1.0 / Aug. 2009
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