HMT312S6DFR6A Datasheet, PDF (20/48 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered SODIMMs Based on 2Gb D-die

Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
DDR3L-800, 1066, 1333, 1600
Min
Max
V_IX(CK)
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
-150
150
V_IX(DQS)
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
150
Notes:
1.The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL  25mV 
VSEH - ((VDD/2) + Vix (Max))  25mV
Unit Notes
mV 2
mV 2
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3L Device Operation” for single-ended
slew rate definitions for address and command signals.

See 7.6 “Data Setup, Hold and Slew Rate Derating” in “DDR3L Device Operation” for single-ended slew
rate definition for data signals.
Rev. 1.1 / Sep. 2012
20