HYMD232G726BL8M-M Datasheet, PDF (2/17 Pages) Hynix Semiconductor – Low Profile Registered DDR SDRAM DIMM

DESCRIPTION
32Mx72 bits
Low Profile Registered DDR SDRAM DIMM
HYMD232G726B(L)8M-M/K/H/L
Hynix HYMD232G726B(L)8M-M/K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM
Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix
HYMD232G726B(L)8M-M/K/H/L series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin
glass-epoxy substrate. Hynix HYMD232G726B(L)8M-M/K/H/L series provide a high performance 8-byte interface in
5.25" width form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD232G726B(L)8M-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232G726B(L)8M-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 256MB (32M x 72) Low Profile Registered DDR
DIMM
• Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
• based on 32Mx8 DDR SDRAM
• Programmable CAS Latency 2 / 2.5 supported
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Error Check Correction (ECC) Capability
• tRAS Lock-out function supported
• Registered inputs with one-clock delay
• Internal four bank operations with single pulsed RAS
• Phase-lock loop (PLL) clock driver to reduce loading • Auto refresh and self refresh supported
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• 8192 refresh cycles / 64ms
• All inputs and outputs are compatible with SSTL_2
interface
ORDERING INFORMATION
Part No.
HYMD232G726B(L)8M-M
HYMD232G726B(L)8M-K
HYMD232G726B(L)8M-H
HYMD232G726B(L)8M-L
Power Supply
Clock Frequency
VDD=2.5V
VDDQ=2.5V
133MHz (*DDR266:2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
Interface
Form Factor
SSTL_2
184pin Low Profile Regis-
tered DIMM
5.25 x 1.2 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Dec. 2003
2