HY5DU283222BF Datasheet, PDF (2/30 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

1HY5DU283222BF(P)
Revision History
No.
History
0.1 1) Defined Target Spec.
0.2 1) Added 200MHz speed bin
0.3
1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/
250Mhz speed bin
0.4 ^{1) Changed IDD & 500Mhz speed bin insert,}
2) Changed tRCDWR, tWR at 450Mhz speed bin
1.0 ^{1) Changed IDD Spec.}
2) Changed CAS Latency to 4 clock from 5 clock at 350MHz speed bin
1.1 _{tWR/ tDAL Changed at 200Mhz}
1.2 IDD6 change
Draft Date
Jun. 2004
Jun. 2004
Remark
Sep. 2004
Oct. 2004
Feb. 2005
May. 2005
Jul. 2005
Rev. 1.2 / Jul. 2005
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