HYMD232646A8J-J Datasheet, PDF (17/18 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD232646A8J
SERIAL PRESENCE DETECT
Bin Sort : J(DDR333@CL=2.5), D4/D43(DDR400@CL=3)
Byte#
Function Description
0
Number of Bytes written into serial memory at module manufac-
turer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9
DDR SDRAM cycle time at CAS Latency=2.5(tCK)@DDR333,
3(tCK)@DDR400
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=2.0(tCK), 2.5(tCK)
24 DDR SDRAM access time from clock at CL=2.0(tAC), 2.5(tAC)
25 DDR SDRAM cycle time at CL=1.5(tCK), 2.0(tCK)
26 DDR SDRAM access time from clock at CL=1.5(tAC), 2.0(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh time ( tRC)
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
43 Maximum cycle time (tCK max)
44 Maximim DQS-DQ skew time(tDQSQ)
45 Maximum read data hold skew factor(tQHS)
46~61 Superset information(Reserved for IDD values, Tcase, etc.)
62 SPD Revision code
63 Checksum for Bytes 0~62
64 Manufacturer JEDEC ID Code
65~71 --------- Manufacturer JEDEC ID Code
Function Supported
D43
D4
J
128 Bytes
256 Bytes
DDR SDRAM
13
10
1Bank
64 Bits
-
SSTL 2.5V
5.0ns 5.0ns 6.0ns
+/-0.7ns
Non-ECC
7.8us & Self refresh
x8
N/A
1 CLK
2,4,8
4 Banks
2, 2.5, 3 2, 2.5, 3 2, 2.5
0
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
6ns
6ns
7.5ns
+/-0.7ns +/-0.7ns +/-0.7ns
7.5ns 7.5ns
-
+/-0.75ns +/-0.75ns
-
15ns
18ns
18ns
10ns
10ns
12ns
15ns
18ns
18ns
40ns
40n
42ns
256MB
0.6ns 0.6ns 0.75ns
0.6ns 0.6ns 0.75ns
0.4ns 0.4ns 0.45ns
0.4ns 0.4ns 0.45ns
Undefined
55ns
58ns
60ns
70ns
70ns
72ns
10ns
10ns
12ns
0.4ns 0.4ns 0.45ns
0.50ns 0.50ns 0.55ns
Undefined
Initial release
-
Hynix JEDEC ID
-
Hexa Value
D43
D4
J
80h
08h
07h
0Dh
0Ah
01h
40h
00h
04h
50h
50h
60h
70h
00h
82h
08h
00h
01h
0Eh
04h
1Ch
1Ch
0Ch
01h
02h
20h
C0h
60h
60h
75h
70h
70h
70h
75h
75h
00h
75h
75h
00h
3Ch
48h
48h
28h
28h
30h
3Ch
48h
48h
28h
28h
2Ah
40h
60h
60h
75h
60h
60h
75h
40h
40h
45h
40h
40h
45h
00h
37h
3Ah
3Ch
46h
46h
48h
28h
28h
30h
28h
28h
2Dh
50h
50h
55h
00h
00h
66h
81h
00h
ADh
00h
Note
1
1
2
2
2
2
2
2
Rev. 0.2 / Apr. 2003
17