H5TQ1G83EFR Datasheet, PDF (16/33 Pages) Hynix Semiconductor – 1Gb DDR3 SDRAM

Symbol
Active Power-Down Current
Description
I_DD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0
Operating Burst Read Current
I_DD4R
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between RD; Command,
Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer
and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
I_DD4W
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between WR; Command,
Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-
fer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
I_DD5B
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8^a); AL: 0; CS: High between REF; Com-
mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID-LEVEL; DM:
stable at 0; Bank Activity: REF command every nREC (see Table 9); Output Buffer and RTT: Enabled in
Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
I_DD6
T_CASE: 0 - 85 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Normal^e);
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command, Address,
Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-
put Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: MID-LEVEL
Self-Refresh Current: Extended Temperature Range
I_DD6ET
T_CASE: 0 - 95 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Extend-
ed^e); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-
ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: MID-
LEVEL
Rev. 1.1 /Aug. 2013
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