HYMD132645B8J-J Datasheet, PDF (15/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD132645B(L)8J-J
SERIAL PRESENCE DETECT
Bin Sort : J(DDR333@CL=2.5)
Byte#
Function Description
Function Supported
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36~40
41
42
43
44
45
46~61
62
63
64
65~71
Number of Bytes written into serial memory at module manufacturer
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of physical banks on DIMM
Module data width
Module data width (continued)
Module voltage Interface levels(VDDQ)
DDR SDRAM cycle time at CAS Latency =2.5(tCK)
DDR SDRAM access time from clock at CL=2.5 (tAC)
Module configuration type
Refresh rate and type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
address(tCCD)
Burst lengths supported
Number of banks on each DDR SDRAM
CAS latency supported
CS latency
WE latency
DDR SDRAM module attributes
DDR SDRAM device attributes : General
DDR SDRAM cycle time at CL=2.0(tCK)
DDR SDRAM access time from clock at CL=2.0(tAC)
DDR SDRAM cycle time at CL=1.5(tCK)
DDR SDRAM access time from clock at CL=1.5(tAC)
Minimum row precharge time(tRP)
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
Data signal input hold time(tDH)
Reserved for VCSDRAM
Minimum active / auto-refresh Time (tRC)
Minimum auto-refresh to active / auto-refresh command
period(tRFC)
Maximum cycle time (tCK max)
Maximum DQS-DQ skew time (tDQSQ)
Maximum read data hold skew factor (tQHS)
Superset Information(may be used in future)
SPD Revision code
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
------ Manufacturer JEDEC ID Code
128 Bytes
256 Bytes
DDR SDRAM
12
10
2Bank
64 Bits
-
SSTL 2.5V
6.0ns
+/-0.7ns
Non-ECC
15.6us & Self refresh
x8
N/A
1 CLK
2,4,8
4 Banks
2, 2.5
0
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
7.5ns
+/-0.7ns
-
-
18ns
12ns
18ns
42ns
128MB
0.75ns
0.75ns
0.45ns
0.45ns
Undefined
60ns
72ns
12ns
0.45ns
0.55ns
Undefined
Initial release
-
Hynix JEDEC ID
-
Rev. 0.1/Jun. 02
Hexa Value
80h
08h
07h
0Ch
0Ah
02h
40h
00h
04h
60h
70h
00h
80h
08h
00h
01h
0Eh
04h
0Ch
01h
02h
20h
C0h
75h
70h
00h
00h
48h
30h
48h
2Ah
20h
75h
75h
45h
45h
00h
3Ch
48h
30h
2Dh
55h
00h
00h
DEh
ADh
00h
Note
1
1
2
2
15