HMT451R7AFR8A Datasheet, PDF (14/72 Pages) Hynix Semiconductor – DDR3L SDRAM Registered DIMM Based on 4Gb A-die

8GB, 1Gx72 Module(1Rank of x4) - page2
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
1:2 ^{RS1A → CS1: SDRAMs D[12:9], D17}
R
E
G
RS1B → CS1: SDRAMs D[16:13]
RRBBAA[[NN::00]]AB
→ BA[N:0]: SDRAMs D[3:0], D[12:8], D17
→ BA[N:0]: SDRAMs D[7:4], D[16:13]
RRAA[[NN::00]]AB
→
→
A[N:0]:
A[N:0]:
SDRAMs
SDRAMs
D[3:0],
D[7:4],
D[12:8], D17
D[16:13]
I
S
T
RRASA → RAS: SDRAMs D[3:0], D[12:8], D17
RRASB → RAS: SDRAMs D[7:4], D[16:13]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D17
RCASB → CAS: SDRAMs D[7:4], D[16:13]
E
RWEA → WE: SDRAMs D[3:0], D[12:8], D17
R
RWEB → WE: SDRAMs D[7:4], D[16:13]
/
PLL
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8]. D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
CK0
PAR_IN
RESET
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
OERR Err_Out
RST
RST: SDRAMs D[17:0]
* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330 resistor to ground.)
Rev. 0.1 / Jul. 2012
14