HY5DU561622FLFP-D5I Datasheet, PDF (12/27 Pages) Hynix Semiconductor – 256Mb DDR SDRAM

HY5DU561622F(L)FP-xxI
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until reset by another MRS command.
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
Operating Mode
CAS Latency
BT
Burst Length
BA0 MRS Type
0
MRS
1
EMRS
A6 A5 A4 CAS Latency
000
Reserved
001
Reserved
010
2
011
3
100
Reserved
101
1.5
110
2.5
111
Reserved
A12~A9 A8 A7 A6~A0
0
0 0 Valid
0
1 0 Valid
0
01
VS
-
--
-
Operating Mode
Normal Operation
Normal Operation/ Reset DLL
Vendor specific Test Mode
All other states reserved
A3 Burst Type
0
Sequential
1
Interleave
Burst Length
A2 A1 A0
Sequential Interleave
0 0 0 Reserved Reserved
001
2
2
010
4
4
011
8
8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
Rev. 1.0 /Nov. 2007
12