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HMT84GL7MMR4A Datasheet, PDF (12/34 Pages) Hynix Semiconductor – DDR3L SDRAM Load Reduced DIMM Based on 4Gb M-die | |||
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32GB, 4Gx72 Module(4Rank of x4) - page3
CS[3:0]
BA[2:0]
A[15:0]
RAS
CAS
WE
CKE[3:0]
ODT[1:0]
CK0
CK0
CK1
CK1
PAR_IN
RESET
CS2A â CS0: SDRAMs D[8:0] CS3A â CS0: SDRAMs D[35:27]
CS0A â CS1: SDRAMs D[8:0] CS1A â CS1: SDRAMs D[35:27]
M
e
m
o
CS2B â CS0: SDRAMs D[17:9] CS3B â CS0: SDRAMs D[26:18]
CS0B â CS1: SDRAMs D[17:9] CS1B â CS1: SDRAMs D[26:18]
BA[2:0]A â BA[2:0]: SDRAMs D[8:0], D[35:27]
BA[2:0]B â BA[2:0]: SDRAMs D[26:9]
r
y
A[15:0]A â A[15:0]: SDRAMs D[8:0], D[35:27]
A[15:0]B â A[15:0]: SDRAMs D[26:9]
RASA â RAS: SDRAMs D[8:0], D[35:27]
RASB â RAS: SDRAMs D[26:9]
B
CASA â CAS: SDRAMs D[8:0], D[35:27]
u
CASB â CAS: SDRAMs D[26:9]
f
WEA â WE: SDRAMs D[8:0], D[35:27]
f
WEB â We: SDRAMs D[26:9]
e
CKE2A â CKE0: D[8:0] CKE0A â CKE1: D[8:0]
r
CKE3A â CKE0: D[26:18] CKE1A â CKE1: D[26:18]
CKE2B â CKE0: D[17:9] CKE0B â CKE1: D[17:9]
CKE3B â CKE0: D[35:27] CKE1B â CKE1: D[35:27]
ODT0A â ODT1: SDRAMs D[8:0]
ODT1A â ODT1: SDRAMs D[35:27]
ODT0B â ODT1: SDRAMs D[17:9]
ODT1B â ODT1: SDRAMs D[26:18]
CK0 â CK: SDRAMs D[8:0]
CK1 â CK: SDRAMs D[35:27]
CK2 â CK: SDRAMs D[17:9]
CK3 â CK: SDRAMs D[26:18]
CK0 â CK: SDRAMs D[8:0]
CK1 â CK: SDRAMs D[35:27]
CK2 â CK: SDRAMs D[17:9]
CK3 â CK: SDRAMs D[26:18]
Err_Out
QRESET: All SDRAMs
1. CK0 and CK0 are terminated with 120 Ohms ±5% resistor.
2. CK1 and CK1 are terminated with 120 Ohms ±5% resistor, but is not used.
3. Unless othersiwe noted resistors are 22 Ohms ±5%
Rev. 1.0 / Jan. 2013
12
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